Static random access memory (SRAM) devices are well-suited for providing working data storage, such as cache memory for processors. Recent system on a chip (SOC) designs often incorporate one, two or more “core processors,” which are predesigned processors such as DSP's, RISC or ARM microprocessors, for example. These core processors are often arranged with a level one (L1) cache memory of SRAM cells laid out near or adjacent to the processor to enable fast processor operations. In many devices in which a dual-core approach is used, such as a radio transceiver integrated circuit, for example, at least one of the radio transceiver's cores may be implemented as a microprocessor core. Several SRAM arrays, each array including a plurality of bit cells, may be used in such integrated circuits.